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CY14B108L CY14B108N
8-Mbit (1024 K x 8/512 K x 16) nvSRAM
8 Mbit (1024K x 8/512K x 16) nvSRAM
Features

20 ns, 25 ns, and 45 ns access times Internally organized as 1024 K x 8 (CY14B108L) or 512 K x16 (CY14B108N) Hands off automatic STORE on power-down with only a small capacitor STORE to QuantumTrap nonvolatile elements initiated by software, device pin, or AutoStore on power-down RECALL to SRAM initiated by software or power-up Infinite Read, Write, and RECALL cycles 1 million STORE cycles to QuantumTrap 20 year data retention Single 3 V +20%, -10% operation Industrial temperature
Packages 44-/54-pin thin small outline package (TSOP-II) 48-ball fine-pitch ball grid array (FBGA) Pb-free and restriction of hazardous substances (RoHS) compliant
Functional Description
The Cypress CY14B108L/CY14B108N is a fast static RAM (SRAM), with a nonvolatile element in each memory cell. The memory is organized as 1024 Kbytes of 8 bits each or 512 K words of 16 bits each. The embedded nonvolatile elements incorporate QuantumTrap technology, producing the world's most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while independent nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power-down. On power-up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control.
VCC VCAP
Logic Block Diagram[1, 2, 3]
Quatrum Trap 2048 X 2048 X 2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A17 A18 A19 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 A9 A10 A11 A12 A13 A14 A15 A16 I N P U T B U F F E R S R O W D E C O D E R STATIC RAM ARRAY 2048 X 2048 X 2 STORE RECALL
POWER CONTROL STORE/RECALL CONTROL SOFTWARE DETECT
HSB
A14 - A2
COLUMN I/O
COLUMN DEC
OE WE
CE BLE
BHE
Notes 1. Address A0 - A19 for x8 configuration and Address A0 - A18 for x16 configuration. 2. Data DQ0 - DQ7 for x8 configuration and Data DQ0 - DQ15 for x16 configuration. 3. BHE and BLE are applicable for x16 configuration only.
Cypress Semiconductor Corporation Document #: 001-45523 Rev. *I
*
198 Champion Court
*
San Jose, CA 95134-1709
* 408-943-2600 Revised March 9, 2011
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Contents
Pinouts .............................................................................. 3 Device Operation .............................................................. 5 SRAM Read ....................................................................... 5 SRAM Write ....................................................................... 5 AutoStore Operation ........................................................ 5 Hardware STORE Operation............................................ 5 Hardware RECALL (Power-Up) ....................................... 6 Software STORE ............................................................... 6 Software RECALL............................................................. 6 Preventing AutoStore....................................................... 8 Data Protection ................................................................. 8 Noise Considerations....................................................... 8 Best Practices................................................................... 8 Maximum Ratings............................................................. 9 Operating Range............................................................... 9 DC Electrical Characteristics .......................................... 9 AC Test Conditions ........................................................ 10 Data Retention and Endurance ..................................... 10 Capacitance .................................................................... 10 Thermal Resistance........................................................ 10 AC Switching Characteristics ....................................... 11 Switching Waveforms .................................................... 11 AutoStore/Power-Up RECALL....................................... Switching Waveforms .................................................... Software Controlled STORE/RECALL Cycle................ Switching Waveforms .................................................... Hardware STORE Cycle ................................................. Switching Waveforms .................................................... Truth Table For SRAM Operations................................ For x8 Configuration ................................................. For x16 Configuration ............................................... Ordering Information...................................................... Ordering Code Definition........................................... Package Diagrams.......................................................... Acronyms ........................................................................ Document Conventions ................................................. Units of Measure ....................................................... Document History Page ................................................. Sales, Solutions, and Legal Information ...................... Worldwide Sales and Design Support....................... Products .................................................................... PSoC Solutions ......................................................... 14 14 15 15 16 16 17 17 17 18 18 19 22 22 22 23 24 24 24 24
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Pinouts
Figure 1. Pin Diagram - 48-Ball FBGA
(x8)
Top View (not to scale)
1 NC NC DQ0 VSS VCC DQ3 NC A18 2 OE NC NC DQ1 DQ2 NC HSB A8 3 A0 A3 A5 A17 VCAP A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE NC DQ5 DQ6 NC WE A11 6 NC NC DQ4 VCC VSS DQ7 NC A19 A B C D E F G H
(x16)
Top View (not to scale)
1 BLE DQ8 2 OE BHE 3 A0 A3 A5 A17 VCAP A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE DQ1 DQ3 DQ4 DQ5 WE A11 6 NC DQ0 DQ2 VCC VSS DQ6 DQ7 NC A B C D E F G H
DQ9 DQ10 VSS DQ11
VCC DQ12 DQ14 DQ13 DQ15 HSB A18 A8
Figure 2. Pin Diagram - 44/54-Pin TSOP II
44-TSOP II
(x8)
54-TSOP II
(x16)
NC [4] NC A0 A1 A2 A3 A4 CE DQ0 DQ1 VCC VSS DQ2 DQ3 WE A5 A6 A7 A8 A9 NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
Top View (not to scale)
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
HSB NC A19 A18 A17 A16 A15 OE DQ7 DQ6 VSS VCC DQ5 DQ4 VCAP A14 A13 A12 A11 A10 NC NC
NC [4] NC A0 A1 A2 A3 A4 CE DQ0 DQ1 DQ2 DQ3 VCC VSS DQ4 DQ5 DQ6 DQ7 WE A5 A6 A7 A8 A9 NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
Top View (not to scale)
HSB A18 A17 A16 A15 OE BHE BLE DQ15 DQ14 DQ13 DQ12 VSS VCC DQ11 DQ10 DQ9 DQ8 VCAP A14 A13 A12 A11 A10 NC NC NC
Note 4. Address expansion for 16 Mbit. NC pin not connected to die.
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Table 1. Pin Definitions Pin Name A0 - A19 A0 - A18 DQ0 - DQ7 DQ0 - DQ15 WE CE OE BHE BLE VSS VCC HSB Input Input Input Input Input Ground I/O Type Input Description Address inputs. Used to select one of the 1,048,576 bytes of the nvSRAM for x8 configuration. Address inputs. Used to select one of the 524,288 words of the nvSRAM for x16 configuration. Input/Output Bidirectional data I/O lines for x8 configuration. Used as input or output lines depending on operation. Bidirectional data I/O lines for x16 configuration. Used as input or output lines depending on operation. Write Enable input, Active LOW. When selected LOW, data on the I/O pins is written to the specific address location. Chip Enable input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles. I/O pins are tristated on deasserting OE HIGH. Byte High Enable, Active LOW. Controls DQ15 - DQ8. Byte Low Enable, Active LOW. Controls DQ7 - DQ0. Ground for the device. Must be connected to the ground of the system.
Power supply Power supply inputs to the device. Input/Output Hardware STORE Busy (HSB). When LOW this output indicates that a Hardware STORE is in progress. When pulled LOW external to the chip it initiates a nonvolatile STORE operation. After each Hardware and Software STORE operation, HSB is driven HIGH for a short time (tHHHD) with standard output high current and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection optional). Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to nonvolatile elements. No connect No connect. This pin is not connected to the die.
VCAP NC
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Device Operation
The CY14B108L/CY14B108N nvSRAM is made up of two functional components paired in the same physical cell. They are a SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to the SRAM (the RECALL operation). Using this unique architecture, all cells are stored and recalled in parallel. During the STORE and RECALL operations, SRAM read and write operations are inhibited. The CY14B108L/CY14B108N supports infinite reads and writes similar to a typical SRAM. In addition, it provides infinite RECALL operations from the nonvolatile cells and up to 1 million STORE operations. See the "Truth Table For SRAM Operations" on page 17 for a complete description of read and write modes.
capacitor on VCAP pin, the device attempts an AutoStore operation without sufficient charge to complete the Store. This corrupts the data stored in nvSRAM. Figure 3 shows the proper connection of the storage capacitor (VCAP) for automatic STORE operation. Refer to DC Electrical Characteristics on page 9 for the size of VCAP. The voltage on the VCAP pin is driven to VCC by a regulator on the chip. A pull-up should be placed on WE to hold it inactive during power-up. This pull-up is effective only if the WE signal is tristate during power-up. Many MPUs tristate their controls on power-up. This should be verified when using the pull-up. When the nvSRAM comes out of power-on-RECALL, the MPU must be active or the WE held inactive until the MPU comes out of reset. To reduce unnecessary nonvolatile STOREs, AutoStore and Hardware STORE operations are ignored unless at least one write operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a write operation has taken place. The HSB signal is monitored by the system to detect if an AutoStore cycle is in progress. Figure 3. AutoStore Mode
VCC
SRAM Read
The CY14B108L/CY14B108N performs a read cycle when CE and OE are LOW and WE and HSB are HIGH. The address specified on pins A0-19 or A0-18 determines which of the 1,048,576 data bytes or 524,288 words of 16 bits each are accessed. Byte enables (BHE, BLE) determine which bytes are enabled to the output, in the case of 16-bit words. When the read is initiated by an address transition, the outputs are valid after a delay of tAA (read cycle 1). If the read is initiated by CE or OE, the outputs are valid at tACE or at tDOE, whichever is later (read cycle 2). The data output repeatedly responds to address changes within the tAA access time without the need for transitions on any control input pins. This remains valid until another address change or until CE or OE is brought HIGH, or WE or HSB is brought LOW.
0.1 uF 10 kOhm VCC
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB is HIGH. The address inputs must be stable before entering the write cycle and must remain stable until CE or WE goes HIGH at the end of the cycle. The data on the common I/O pins DQ0-15 are written into the memory if the data is valid tSD before the end of a WE controlled write or before the end of an CE controlled write. The Byte Enable inputs (BHE, BLE) determine which bytes are written, in the case of 16-bit words. Keep OE HIGH during the entire write cycle to avoid data bus contention on common I/O lines. If OE is left LOW, internal circuitry turns off the output buffers tHZWE after WE goes LOW.
WE
VCAP VCAP
VSS
Hardware STORE Operation
The CY14B108L/CY14B108N provides the HSB pin to control and acknowledge the STORE operations. Use the HSB pin to request a Hardware STORE cycle. When the HSB pin is driven LOW, the CY14B108L/CY14B108N conditionally initiates a STORE operation after tDELAY. An actual STORE cycle only begins if a write to the SRAM has taken place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver (internal 100 k weak pull-up resistor) that is internally driven LOW to indicate a busy condition when the STORE (initiated by any means) is in progress. Note After each Hardware and Software STORE operation HSB is driven HIGH for a short time (tHHHD) with standard output high current and then remains HIGH by internal 100 k pull-up resistor.
AutoStore Operation
The CY14B108L/CY14B108N stores data to the nvSRAM using one of the following three storage operations: Hardware STORE activated by the HSB; Software STORE activated by an address sequence; AutoStore on device power-down. The AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the CY14B108L/CY14B108N. During a normal operation, the device draws current from VCC to charge a capacitor connected to the VCAP pin. This stored charge is used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part automatically disconnects the VCAP pin from VCC. A STORE operation is initiated with power provided by the VCAP capacitor. Note If the capacitor is not connected to VCAP pin, AutoStore must be disabled using the soft sequence specified in Preventing AutoStore on page 8. In case AutoStore is enabled without a Document #: 001-45523 Rev. *I
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SRAM write operations that are in progress when HSB is driven LOW by any means are given time (tDELAY) to complete before the STORE operation is initiated. However, any SRAM write cycles requested after HSB goes LOW are inhibited until HSB returns HIGH. In case the write latch is not set, HSB is not driven LOW by the CY14B108L/CY14B108N. But any SRAM read and write cycles are inhibited until HSB is returned HIGH by MPU or other external source. During any STORE operation, regardless of how it is initiated, the CY14B108L/CY14B108N continues to drive the HSB pin LOW, releasing it only when the STORE is complete. Upon completion of the STORE operation, the nvSRAM memory access is inhibited for tLZHSB time after HSB pin returns HIGH. Leave the HSB unconnected if it is not used.
1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x8FC0 Initiate STORE cycle The software sequence may be clocked with CE controlled reads or OE controlled reads, with WE kept HIGH for all the six READ sequences. After the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. HSB is driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is activated again for the read and write operation.
Hardware RECALL (Power-Up)
During power-up or after any low power condition (VCC< VSWITCH), an internal RECALL request is latched. When VCC again exceeds the VSWITCH on power-up, a RECALL cycle is automatically initiated and takes tHRECALL to complete. During this time, the HSB pin is driven LOW by the HSB driver and all reads and writes to nvSRAM are inhibited.
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of read operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of CE or OE controlled read operations must be performed. 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x4C63 Initiate RECALL cycle Internally, RECALL is a two-step procedure. First, the SRAM data is cleared; then, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is again ready for read and write operations. The RECALL operation does not alter the data in the nonvolatile elements.
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by a software address sequence. The CY14B108L/CY14B108N Software STORE cycle is initiated by executing sequential CE or OE controlled read cycles from six specific address locations in exact order. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. After a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence, or the sequence is aborted and no STORE or RECALL takes place. To initiate the Software STORE cycle, the following read sequence must be performed.
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Table 2. Mode Selection CE H L L L WE X H L H OE X L X L BHE, BLE[5] X L L X A15 - A0[6] X X X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8B45 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4B46 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8FC0 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4C63 Mode Not Selected Read SRAM Write SRAM Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Disable Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Enable Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL I/O Output High Z Output data Input data Output data Output data Output data Output data Output data Output data Output data Output data Output data Output data Output data Output data Output data Output data Output data Output data Output data Output High Z Output data Output data Output data Output data Output data Output High Z Power Standby Active Active Active[7]
L
H
L
X
Active[7]
L
H
L
X
Active ICC2[7]
L
H
L
X
Active[7]
Notes 5. BHE and BLE are applicable for x16 configuration only. 6. While there are 20 address lines on the CY14B108L (19 address lines on the CY14B108N), only the 13 address lines (A14 - A2) are used to control software modes. Rest of the address lines are don't care. 7. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
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Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore disable sequence. A sequence of read operations is performed in a manner similar to the Software STORE initiation. To initiate the AutoStore disable sequence, the following sequence of CE or OE controlled read operations must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x8B45 AutoStore Disable The AutoStore is re-enabled by initiating an AutoStore enable sequence. A sequence of read operations is performed in a manner similar to the Software RECALL initiation. To initiate the AutoStore enable sequence, the following sequence of CE or OE controlled read operations must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x4B46 AutoStore Enable If the AutoStore function is disabled or re-enabled, a manual STORE operation (Hardware or Software) must be issued to save the AutoStore state through subsequent power-down cycles. The part comes from the factory with AutoStore enabled.
Noise Considerations
Refer to CY application note AN1064.
Best Practices
nvSRAM products have been used effectively for over 27 years. While ease-of-use is one of the product's main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices:
The nonvolatile cells in this nvSRAM product are delivered from Cypress with 0x00 written in all cells. Incoming inspection routines at customer or contract manufacturer's sites sometimes reprogram these values. Final NV patterns are typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End product's firmware should not assume an NV array is in a set programmed state. Routines that check memory content values to determine first time system configuration, cold or warm boot status, and so on should always program a unique NV pattern (that is, complex 4-byte pattern of 46 E6 49 53 hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently. power-up boot firmware routines should rewrite the nvSRAM into the desired state (for example, AutoStore enabled). While the nvSRAM is shipped in a preset state, best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently such as program bugs and incoming inspection routines. The VCAP value specified in this data sheet includes a minimum and a maximum value size. Best practice is to meet this requirement and not exceed the maximum VCAP value because the nvSRAM internal algorithm calculates VCAP charge and discharge time based on this maximum VCAP value. Customers that want to use a larger VCAP value to make sure there is extra store charge and store time should discuss their VCAP size selection with Cypress to understand any impact on the VCAP voltage level at the end of a tRECALL period.
Data Protection
The CY14B108L/CY14B108N protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and write operations. The low voltage condition is detected when VCC < VSWITCH. If the CY14B108L/CY14B108N is in a write mode (both CE and WE are LOW) at power-up, after a RECALL or STORE, the write is inhibited until the SRAM is enabled after tLZHSB (HSB to output active). This protects against inadvertent writes during power-up or brown out conditions.
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Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ................................ -65 C to +150 C Maximum accumulated storage time At 150 C ambient temperature..........................1000 h At 85 C ambient temperature.................... .. 20 Years Ambient temperature with power applied ........................................... -55 C to +150 C Supply voltage on VCC relative to VSS ............-0.5 V to 4.1 V Voltage applied to outputs in High-Z state ..................................... -0.5 V to VCC + 0.5 V Input voltage .........................................-0.5 V to Vcc + 0.5 V Transient voltage (<20 ns) on any pin to ground potential .................. -2.0 V to VCC + 2.0 V Package power dissipation capability (TA = 25 C) ................................................. .1.0 W Surface mount Pb soldering temperature (3 Seconds).......................................... +260 C DC output current (1 output at a time, 1s duration) ..... 15 mA Static discharge voltage.......................................... > 2001 V (per MIL-STD-883, Method 3015) Latch up current..................................................... > 200 mA
Operating Range
Range Industrial Ambient Temperature -40 C to +85 C VCC 2.7 V to 3.6 V
DC Electrical Characteristics
Over the Operating Range (VCC = 2.7 V to 3.6 V) Parameter Description VCC ICC1 Power supply Average VCC current tRC = 20 ns tRC = 25 ns tRC = 45 ns Values obtained without output loads (IOUT = 0 mA) Average VCC current All inputs don't care, VCC = Max during STORE Average current for duration tSTORE Average VCC current All inputs cycling at CMOS levels. Values obtained without output loads (IOUT = 0 mA). at tRC= 200 ns, VCC (Typ), 25 C Average VCAP current All inputs don't care. Average current for duration tSTORE during AutoStore cycle VCC standby current CE > (VCC - 0.2 V). VIN < 0.2 V or > (VCC - 0.2 V). Standby current level after nonvolatile cycle is complete. Inputs are static. f = 0 MHz. Input leakage current VCC = Max, VSS < VIN < VCC (except HSB) Input leakage current VCC = Max, VSS < VIN < VCC (for HSB) IOZ VIH VIL VOH VOL VCAP Off-state output leakage current Input HIGH voltage Input LOW voltage Output HIGH voltage IOUT = -2 mA Output LOW voltage IOUT = 4 mA Storage capacitor Between VCAP pin and VSS, 5 V Rated VCC = Max, VSS < VOUT < VCC, CE or OE > VIH or BHE/BLE > VIH or WE < VIL Test Conditions Min 2.7 - Typ[8] 3.0 - Max 3.6 75 75 57 20 - Unit V mA mA mA mA mA
ICC2 ICC3
- -
- 40
ICC4
-
-
10
mA
ISB IIX[9]
-
-
10
mA
-2 -200 -2 2.0 Vss - 0.5 2.4 - 122
- - - - - - - 150
+2 +2 +2 VCC + 0.5 0.8 - 0.4 360
A A A V V V V F
Notes 8. Typical values are at 25C, VCC= VCC (Typ). Not 100% tested. 9. The HSB pin has IOUT = -2 uA for VOH of 2.4 V when both active HIGH and LOW drivers are disabled. When they are enabled standard VOH and VOL are valid. This parameter is characterized but not tested.
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Data Retention and Endurance
Parameter DATAR NVC Data retention Nonvolatile STORE operations Description Min 20 1,000 Unit Years K
Capacitance
In the following table, the capacitance parameters are listed.[10] Parameter CIN COUT Description Input capacitance Output capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = VCC (Typ) Max 14 14 Unit pF pF
Thermal Resistance
Parameter
In the following table, the thermal resistance parameters are listed. [10] Description Thermal resistance (Junction to ambient) Thermal resistance (Junction to case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. Figure 4. AC Test Loads 48-FBGA 44-TSOP II 54-TSOP II 42.2 6.3 45.3 5.2 44.22 8.26 Unit C/W C/W
JA JC
3.0 V OUTPUT 30 pF
577 R1 R2 789
3.0 V OUTPUT 5 pF
577 R1
for tristate specs
R2 789
AC Test Conditions
Input pulse levels.................................................... 0 V to 3 V Input rise and fall times (10% - 90%) ........................... <3 ns Input and output timing reference levels ....................... 1.5 V
Note 10. These parameters are guaranteed by design but not tested.
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AC Switching Characteristics
Parameters Description Cypress Alt Parameter Parameter SRAM Read Cycle tACE tACS Chip enable access time tRC[11] tRC Read cycle time [12] tAA tAA Address access time tDOE tOE Output enable to data valid [12] tOHA tOH Output hold after address change tLZCE[13, 14] tLZ Chip enable to output active tHZCE[13, 14] tHZ Chip disable to output inactive [13, 14] tOLZ Output enable to output active tLZOE tHZOE[13, 14] tOHZ Output disable to output inactive tPU[13] tPA [13] tPD tPS tDBE [13] tLZBE tHZBE[13] SRAM Write Cycle tWC tWC tPWE tWP tSCE tCW tSD tDW tHD tDH tAW tAW tSA tAS tHA tWR [13, 14,15] tHZWE tWZ tOW tLZWE[13, 14] tBW Chip enable to power active Chip disable to power standby Byte enable to data valid Byte enable to output active Byte disable to output inactive Write cycle time Write pulse width Chip enable to end of write Data setup to end of write Data hold after end of write Address setup to end of write Address setup to start of write Address hold after end of write Write enable to output disable Output active after end of write Byte enable to end of write 20 ns Min - 20 - - 3 3 - 0 - 0 - - 0 - 20 15 15 8 0 15 0 0 - 3 15 Max 20 - 20 10 - - 8 - 8 - 20 10 - 8 - - - - - - - - 8 - - 25 ns Min - 25 - - 3 3 - 0 - 0 - - 0 - 25 20 20 10 0 20 0 0 3 20 Max 25 - 25 12 - - 10 - 10 - 25 12 - 10 - - - - - - - - 10 - - 45 ns Min - 45 - - 3 3 - 0 - 0 - - 0 - 45 30 30 15 0 30 0 0 - 3 30 Max 45 - 45 20 - - 15 - 15 - 45 20 - 15 - - - - - - - - 15 - - Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Switching Waveforms
Figure 5. SRAM Read Cycle #1: Address Controlled[11, 12, 16]
tRC
Address
Address Valid tAA
Data Output
Previous Data Valid tOHA
Output Data Valid
Notes 11. WE must be HIGH during SRAM read cycles. 12. Device is continuously selected with CE, OE and BHE / BLE LOW. 13. These parameters are guaranteed by design but not tested. 14. Measured 200 mV from steady state output voltage. 15. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state. 16. HSB must remain HIGH during READ and WRITE cycles.
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Figure 6. SRAM Read Cycle #2: CE and OE Controlled[17, 18, 19]
Address Address Valid tACE tAA tLZCE OE tLZOE tDBE BHE, BLE tLZBE Data Output High Impedance tPU Standby Active Output Data Valid tPD tDOE tHZBE tHZOE tRC tHZCE
CE
ICC
Figure 7. SRAM Write Cycle #1: WE Controlled[17, 19, 20, 21]
Notes 17. BHE and BLE are applicable for x16 configuration only. 18. WE must be HIGH during SRAM read cycles. 19. HSB must remain HIGH during READ and WRITE cycles. 20. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state. 21. CE or WE must be >VIH during address transitions.
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Figure 8. SRAM Write Cycle #2: CE Controlled[22, 23, 24, 25]
tWC Address tSA CE tBW BHE, BLE tPWE WE tSD Data Input Data Output Input Data Valid High Impedance tHD Address Valid tSCE tHA
Figure 9. SRAM Write Cycle #3: BHE and BLE Controlled[22, 23, 24, 25]
tWC Address tSCE CE tSA BHE, BLE tAW tPWE WE tSD Data Input Data Output tHD Input Data Valid High Impedance tBW tHA Address Valid
Notes 22. BHE and BLE are applicable for x16 configuration only. 23. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state. 24. HSB must remain HIGH during READ and WRITE cycles. 25. CE or WE must be >VIH during address transitions.
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CY14B108L CY14B108N
AutoStore/Power-Up RECALL
Parameter Description 20 ns Min - - - - 150 - - - Max 20 8 20 2.65 - 1.9 5 500 Min - - - - 150 - - - 25 ns Max 20 8 25 2.65 - 1.9 5 500 Min - - - - 150 - - - 45 ns Max 20 8 25 2.65 - 1.9 5 500 Unit ms ms ns V s V s ns
tHRECALL[26] Power-Up RECALL duration tSTORE
[27]
STORE cycle duration Time allowed to complete SRAM write cycle Low voltage trigger level HSB output disable voltage HSB to output active time HSB high active time
tDELAY [28] VSWITCH VHDIS[29] tLZHSB[29] tHHHD[29]
tVCCRISE[29] VCC rise time
Switching Waveforms
VCC VSWITCH VHDIS
Figure 10. AutoStore or Power-Up RECALL[30]
t VCCRISE Note 31 HSB OUT
tHHHD
Note
27
tSTORE tHHHD tDELAY
Note27
tSTORE Note
31
AutoStore POWERUP RECALL Read & Write Inhibited (RWI)
tLZHSB tDELAY
tLZHSB
tHRECALL
tHRECALL
POWER-UP RECALL
Read & Write
BROWN OUT AutoStore
POWER-UP RECALL
Read & Write
POWER DOWN AutoStore
Notes 26. tHRECALL starts from the time VCC rises above VSWITCH. 27. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place. 28. On a Hardware STORE and AutoStore initiation, SRAM write operation continues to be enabled for time tDELAY. 29. These parameters are guaranteed by design but not tested. 30. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH. 31. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor.
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CY14B108L CY14B108N
Software Controlled STORE/RECALL Cycle
Parameter tRC tSA tCW tHA tRECALL Description STORE/RECALL initiation cycle time Address setup time Clock pulse width Address hold time RECALL duration
In the following table, the software controlled STORE and RECALL cycle parameters are listed.[32, 33] 20 ns Min Max 20 - 0 - 15 - 0 - - 200 25 ns Min Max 25 - 0 - 20 - 0 - - 200 45 ns Min Max 45 - 0 - 30 - 0 - - 200 Unit ns ns ns ns s
Switching Waveforms
Figure 11. CE and OE Controlled Software STORE/RECALL Cycle[33]
tRC tRC Address #6 tCW tHA tHA
Address tSA CE tSA OE
Address #1 tCW
tHA
tHA tHHHD
HSB (STORE only) DQ (DATA)
tLZCE
tHZCE
t DELAY
Note
34
High Impedance tSTORE/tRECALL
tLZHSB
RWI
Figure 12. Autostore Enable/Disable Cycle
tRC Address tSA CE tSA OE tLZCE DQ (DATA) tHZCE tSS Note
34
tRC Address #6 tCW
Address #1 tCW tHA tHA
tHA
tHA
t DELAY
Notes 32. The software sequence is clocked with CE controlled or OE controlled reads. 33. The six consecutive addresses must be read in the order listed in Table 2 on page 7. WE must be HIGH during all six consecutive cycles. 34. DQ output data at the sixth read may be invalid since the output is disabled at tDELAY time.
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CY14B108L CY14B108N
Hardware STORE Cycle
Parameter tDHSB tPHSB tSS [35, 36] Description HSB to output active time when write latch not set Hardware STORE pulse width Soft sequence processing time 20 ns Min - 15 - Max 20 - 100 Min - 15 - 25 ns Max 25 - 100 Min - 15 - 45 ns Max 25 - 100 Unit ns ns s
Switching Waveforms
Figure 13. Hardware STORE Cycle[37]
Write latch set
tPHSB HSB (IN) tDELAY HSB (OUT) DQ (Data Out) RWI tLZHSB tSTORE tHHHD
Write latch not set
tPHSB HSB (IN) HSB pin is driven high to VCC only by Internal 100 kOhm resistor, HSB driver is disabled SRAM is disabled as long as HSB (IN) is driven low. tDELAY tDHSB tDHSB
HSB (OUT) RWI
Figure 14. Soft Sequence Processing[35, 36]
Soft Sequence Command Address Address #1 tSA Address #6 tCW tSS Soft Sequence Command Address #1 Address #6 tCW tSS
CE VCC
Notes 35. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command. 36. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command. 37. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
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Truth Table For SRAM Operations
HSB should remain HIGH for SRAM Operations.
For x8 Configuration
CE H L L L WE X H H L OE X L H X High Z Data out (DQ0-DQ7); High Z Data in (DQ0-DQ7); BHE[39] BLE[39] X H L H L L H L L H L X H L L H L L H L L H Inputs/Outputs[38] Read Output disabled Write Mode Deselect/Power-down Standby Active Active Active Power
For x16 Configuration
CE H L L L L L L L L L L WE X X H H H H H H L L L OE X X L L L H H H X X X Inputs/Outputs[38] High Z High Z Data out (DQ0-DQ15) Data out (DQ0-DQ7); DQ8-DQ15 in High Z Data out (DQ8-DQ15); DQ0-DQ7 in High Z High Z High Z High Z Data in (DQ0-DQ15) Data in (DQ0-DQ7); DQ8-DQ15 in High Z Data in (DQ8-DQ15); DQ0-DQ7 in High Z Mode Deselect/Power-down Output disabled Read Read Read Output disabled Output disabled Output disabled Write Write Write Active Active Active Active Active Active Active Active Active Active Power Standby
Notes 38. Data DQ0 - DQ7 for x8 configuration and Data DQ0 - DQ15 for x16 configuration. 39. BHE and BLE are applicable for x16 configuration only.
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CY14B108L CY14B108N
Ordering Information
Speed (ns) 20 25 Ordering Code CY14B108L-ZS20XIT CY14B108L-ZS20XI CY14B108L-ZS25XIT CY14B108L-ZS25XI CY14B108L-BA25XIT CY14B108L-BA25XI CY14B108N-BA25XIT CY14B108N-BA25XI CY14B108N-ZSP25XIT CY14B108N-ZSP25XI 45 CY14B108L-ZS45XIT CY14B108L-ZS45XI CY14B108L-BA45XIT CY14B108L-BA45XI CY14B108N-BA45XIT CY14B108N-BA45XI CY14B108N-ZSP45XIT CY14B108N-ZSP45XI
All the above parts are Pb-free.
Package Diagram 51-85087 51-85087 51-85087 51-85087 51-85128 51-85128 51-85128 51-85128 51-85160 51-85160 51-85087 51-85087 51-85128 51-85128 51-85128 51-85128 51-85160 51-85160
Package Type 44-pin TSOP II 44-pin TSOP II 44-pin TSOP II 44-pin TSOP II 48-ball FBGA 48-ball FBGA 48-ball FBGA 48-ball FBGA 54-pin TSOP II 54-pin TSOP II 44-pin TSOP II 44-pin TSOP II 48-ball FBGA 48-ball FBGA 48-ball FBGA 48-ball FBGA 54-pin TSOP II 54-pin TSOP II
Operating Range Industrial
Ordering Code Definition
CY 14 B 108 L-ZS 20 X I T Option: T - Tape & Reel Blank - Std. Pb-Free Package: BAp - 48 FBGA ZSP - 44 TSOP II ZSP - 54 TSOP II
Temperature: I - Industrial (-40 to 85 C)
Speed: 20 - 20 ns 25 - 25 ns 45 - 45 ns
Data Bus: L - x8 N - x16
Voltage: B - 3.0 V 14 - NVSRAM Cypress
Density: 108 - 8 Mb
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Package Diagrams
Figure 15. 44-Pin TSOP II (51-85087)
51-85087 *C
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CY14B108L CY14B108N
Package Diagrams
(continued) Figure 16. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm (51-85128)
51-85128 *E
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Package Diagrams
(continued) Figure 17. 54-Pin TSOP II (51-85160)
51-85160 *A
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CY14B108L CY14B108N
Acronyms
Acronym nvSRAM TSOP II FBGA RoHS I/O CMOS EIA RWI Description nonvolatile static random access memory thin small outline package fine-pitch ball grid array restriction of hazardous substances input/output complementary metal oxide semiconductor electronic industries alliance read and write inhibited
Document Conventions
Units of Measure
Symbol C Hz kbit kHz K A mA F MHz s ms ns pF V W hertz 1024 bits kilohertz kilo ohms microamperes milliampere microfarads megahertz microseconds millisecond nanoseconds picofarads volts ohms watts Unit of Measure degrees celsius
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CY14B108L CY14B108N
Document History Page
Document Title: CY14B108L, CY14B108N 8-Mbit (1024 K x 8/512 K x 16) nvSRAM Document Number: 001-45523 Rev. ** *A ECN No. 2428826 2520023 Orig. of Change GVCH GVCH/PYRS Submission Date See ECN 06/23/08 New Data Sheet Updated ICC1 for tRC=20ns, 25ns and 45ns access speed for both industrial and Commercial temperature Grade Updated Thermal resistance values for 48-FBGA,44-TSOP II and 54-TSOP II packages Changed tCW value from 16ns to 15ns Added maximum accumulated storage time for 150C and 85C Temperature Added best practices Changed ICC2 from 12mA to 20mA Changed ICC3 from 38mA to 40mA Changed ICC4 from 12mA to 10mA Changed ISB from 6mA to 10mA Changed VCAP from 164uF to 360uF Changed Input Rise and Fall Times from 5ns to 3ns Updated ICC1, ICC3, ISBand IOZ Test conditions Changed tDELAY to 20ns, 25ns, 25ns for 15ns, 20ns, 45ns part respectively Changed tSTORE from 15ms to 8ms Added VHDIS, tHHHD and tLZHSB parameters Software controlled STORE/RECALL cycle table: Changed tAS to tSA Changed tGHAX to tHA Added tDHSB parameter Changed tHLHX to tPHSB Updated tSS from 70us to 100us Added Truth table for SRAM operations Updated ordering information Moved data sheet status from Preliminary to Final Updated AutoStore operation Updated ISB test condition Updated footnote 7 Referenced footnote 9 to VCCRISE, tHHHD and tLZHSB parameters Updated VHDIS parameter description Page 4: Updated Hardware STORE (HSB) operation description page 5: Updated Software STORE description Updated tDELAY parameter description Updated footnote 18 and added footnote 23 Referenced footnote 23 to Figure 11 and Figure 12 Removed commercial temperature related specs Changed STORE cycles to QuantumTrap from 200K to 1 Million Added Contents on page 2 Removed part numbers CY14B108N-ZSP20XIT and CY14B108N-ZSP20XI from ordering information table. Updated Package diagrams 51-85160 and 51-85087. Updated Sales, Solution, and Legal Information Section. Updated copyright section. Updated table of contents. Table 1: Added more clarity on HSB pin operation Hardware STORE Operation: Added more clarity on HSB pin operation Table 2: Added more clarity on BHE/BLE pin operation Updated HSB pin operation in Figure 10 Updated footnote 31 Description of Change
*B
2676670
GVCH/PYRS
03/20/2009
*C
2712462
GVCH/PYRS
05/29/2009
*D
2746310
GVCH
07/29/2009
*E *F *G
2759948 2828257 2894560
GVCH GVCH GVCH
09/04/2009 12/15/2009 03/18/2010
*H
2923475
GVCH/AESA
04/27/2010
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Document Title: CY14B108L, CY14B108N 8-Mbit (1024 K x 8/512 K x 16) nvSRAM Document Number: 001-45523 Rev. *I ECN No. 3143765 Orig. of Change GVCH Submission Date 01/17/2011 Description of Change 48-ball FBGA package: 16 Mb address expansion is not supported Updated thermal resistance values for all packages Added Acronyms table and Document Conventions table
Sales, Solutions, and Legal Information
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(c) Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-45523 Rev. *I
Revised March 9, 2011
Page 24 of 24
All products and company names mentioned in this document may be the trademarks of their respective holders.
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